Process and Device Technology for Sub-70 Nm Cmos

Synopsis

A video recording of a short course held by the International Electron Devices Meeting (IDEM) in 2001. Moore’s Law inexorably drives the density, size and performance of semiconductors. The feature size of modern silicon technology is at the 130nm node and will soon move to the 100nm node. Prognostications of fundamental limits notwithstanding, device gate lengths will shrink down to 50nm in the 100nm node and equivalent gate oxide thickness will scale below 15A. Further shrinking to the 70nm CMOS technology node in many ways places us at crossroads, and each path is fraught with significant challenges. Maintaining performance trends in sub-50 nm devices will drive novel device architectures such as SOI, SiGe, and vertical devices. Increasing gate leakage currents accompanying the aggressive scaling of gate dielectrics coupled with the low power requirements of mobile products will require new gate dielectrics. The wavelength of light will need to be dialed back another notch to keep up with pattern resolution requirements. This course provides insight into these challenges in the front-end-of-the-line, and discusses potential solutions in the areas of device design, lithography, gate stack, process integration and manufacturing trends. The first lecture covers device scaling trends for both low power and high performance applications. It further covers the device requirements and architectures for the 70nm node including a glimpse at novel structures. The second lecture covers lithography requirements and trends including a discussion of 157nm lithography systems and beyond. The third lecture presents an overview of the materials under consideration to replace the conventional polysilicon/SiO2 (SiON) system and the process integration challenges spawned by this transition. New materials and process integration challenges for device isolation, shallow junction formation and the silicide technology required for contacting the shallow junctions are discussed in detail in the fourth lecture. Finally, not all trends are benefited by the performance and cost driven scaling paradigm. Yield enhancement in particular is made more challenging by the shrinking dimensions. Requirements and trends for efficient manufacturing and yield management are the topic of the final lecture.

Language

English

Country

United States

Year of release

2002

Year of production

2001

Notes

On 4 videocassettes

Subjects

Information technology

Keywords

electronic engineering; materials; microelectronic devices; mobile phones; semiconductors

Distribution Formats

Type

VHS

Format

PAL

Price

$450.00

Availability

Sale

Duration/Size

420 mins

Year

2003

Production Company

Name

International Electron Devices Meeting (IEDM)

Distributor

Name

Institute of Electrical and Electronic Engineers Inc

Email

customer-service@ieee.org

Web

http://www.ieee.org/organizations/eab/ceus/ssvideo.htm External site opens in new window

Phone

+1 908 562 5493

Address

445 Hoes Lane
PO Box 1331
Piscataway
NJ 08855-1331
USA